Difference between revisions of "V.24 Level Shifter Board"
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[[Category:Quantar]] | [[Category:Quantar]] | ||
| + | [[Category:Wireline]] | ||
| + | [[Category:Astro-Tac]] | ||
| + | This is a page about the v.24 level converter I made to be fully drop in replacement for the [[Wireline#v.24_TTN4010|TTN4010 OEM board]]. | ||
| − | + | = Features = | |
| + | * '''Full OEM Compatibility''' - This will work in place of the OEM board | ||
| + | ** Includes a relay so that the station can originate clock '''''OR''''' be clocked by DCE. | ||
| + | * Simple design - Affordable and easy to assemble, only one IC | ||
| + | * The following can be done via dip switch at the RS232 level | ||
| + | ** CD asserted and tied to MARK or SPACE | ||
| + | ** Tie TXCLK and RXCLK together - this allows a station to connect to another which is set to not send TX clock | ||
| + | ** Tie CTS and RTS together - needed in some cases for certain v24 to DCE connections | ||
| + | * Built in cross over port to connect two stations with a standard Ethernet patch cable without needing a crossover adapter. | ||
| + | * Internally ESD (10kv) protected design - meets or exceeds the OEM v.24 daughter card or other designs based on the MC145406 | ||
| + | * Fits in the front or back ports of the Wireline board without contacting or putting pressure on other components on the wireline board. | ||
| + | * Permits adding v.24 interface to quantars without the need to replace/modify faceplate. Cables can be routed out the back. | ||
| + | * Builtin v.24 network tap for debugging (both RJ-45's are connected to the lines.) | ||
| + | * Not a Graham Cracker | ||
| + | |||
| + | == Tested Config == | ||
| + | |||
| + | * Quantar/Quantro base station | ||
| + | * PDR3500 Base station | ||
| + | * AstroTAC 3000 Comparator <ref>this needs the CD line asserted</ref> | ||
| + | |||
| + | Tested with TRN7477, TRN7667, CLN6955, CLN6956 and CLN7343 wireline boards. | ||
| + | |||
| + | = Notes = | ||
| + | |||
| + | The Astro-Tac 3000 needs CD active to put the port active. | ||
= Background info = | = Background info = | ||
https://www.ti.com/lit/an/slla544/slla544.pdf | https://www.ti.com/lit/an/slla544/slla544.pdf | ||
| + | |||
| + | https://www.ti.com/lit/ds/symlink/sn75185.pdf | ||
https://www.analog.com/en/resources/technical-articles/fundamentals-of-rs232-serial-communications.html | https://www.analog.com/en/resources/technical-articles/fundamentals-of-rs232-serial-communications.html | ||
| Line 13: | Line 43: | ||
https://www.analog.com/media/en/technical-documentation/data-sheets/MAX3185.pdf | https://www.analog.com/media/en/technical-documentation/data-sheets/MAX3185.pdf | ||
| + | |||
| + | '''Maxim datasheet has the pin-out wrong on page 5 for the T3IN and T1IN lines.''' This is being resolved, but T3 is 13 and T1 is 16 with the chips i have. This also matches the SN75185 chip that it's designed as drop in replacement for. | ||
good: | good: | ||
https://electronics.stackexchange.com/a/649122 | https://electronics.stackexchange.com/a/649122 | ||
| + | |||
| + | https://www.ti.com/lit/ds/symlink/tl145406.pdf | ||
| + | |||
| + | = Revisions = | ||
| + | |||
| + | == 2024-05-22 == | ||
| + | Pending, ffs lets hope this is it. Switched to the SN75185 part and updated the layout. | ||
| + | |||
| + | == 2024-05-12 == | ||
| + | |||
| + | Discovered the MAX3185 datasheet has pins 13 and 16 swapped on it. All the CAD models have the same swap. After cutting and fixing this, the board works as expected. | ||
| + | |||
| + | Will need to do a respin once Maxim/Analog Devices gets back to me. | ||
| + | |||
| + | == 2024-05-01 == | ||
| + | |||
| + | PCB needs to be respun IO ports are reversed on the IO lines of the level converter. | ||
| + | |||
| + | Change the switch to use RS232 levels vs 5v TTL levels for 2-4. | ||
| + | |||
| + | = Production Testing = | ||
| + | |||
| + | With Quantar set to originate clock | ||
| + | |||
| + | * plug in board, relay should activate | ||
| + | * Verify clock is seen on the TXCLK pin 3 (W/Green) of J2 or pin 1 (W/Orange) of J3. | ||
| + | * Close SW3 and check for clock on RXCLK (W/Orange) of J2 | ||
| + | * Connect using straight through cable from cross port to astrotac v.24 port set to clock from DCE. Check that it is down, but you see data on the TXD line. | ||
| + | * close SW1 to enable CTS and check that Pin 42 CTS of J1 is low and that CTS on J2 is RS232 level high (4-10v) | ||
| + | * close SW2 to tie RTS and CTS and check that RTS and CTS are low on J1 (41 and 42) | ||
| + | * close SW4 to assert CD and see that the link is up between quantar and astrotac. | ||
| + | |||
| + | This should verify everything other than TXCLK input from DCE. | ||
Latest revision as of 18:18, 23 May 2024
This is a page about the v.24 level converter I made to be fully drop in replacement for the TTN4010 OEM board.
Contents
Features
- Full OEM Compatibility - This will work in place of the OEM board
- Includes a relay so that the station can originate clock OR be clocked by DCE.
- Simple design - Affordable and easy to assemble, only one IC
- The following can be done via dip switch at the RS232 level
- CD asserted and tied to MARK or SPACE
- Tie TXCLK and RXCLK together - this allows a station to connect to another which is set to not send TX clock
- Tie CTS and RTS together - needed in some cases for certain v24 to DCE connections
- Built in cross over port to connect two stations with a standard Ethernet patch cable without needing a crossover adapter.
- Internally ESD (10kv) protected design - meets or exceeds the OEM v.24 daughter card or other designs based on the MC145406
- Fits in the front or back ports of the Wireline board without contacting or putting pressure on other components on the wireline board.
- Permits adding v.24 interface to quantars without the need to replace/modify faceplate. Cables can be routed out the back.
- Builtin v.24 network tap for debugging (both RJ-45's are connected to the lines.)
- Not a Graham Cracker
Tested Config
- Quantar/Quantro base station
- PDR3500 Base station
- AstroTAC 3000 Comparator [1]
Tested with TRN7477, TRN7667, CLN6955, CLN6956 and CLN7343 wireline boards.
Notes
The Astro-Tac 3000 needs CD active to put the port active.
Background info
https://www.ti.com/lit/an/slla544/slla544.pdf
https://www.ti.com/lit/ds/symlink/sn75185.pdf
https://www.analog.com/en/products/max3185.html
https://www.analog.com/media/en/technical-documentation/data-sheets/MAX3185.pdf
Maxim datasheet has the pin-out wrong on page 5 for the T3IN and T1IN lines. This is being resolved, but T3 is 13 and T1 is 16 with the chips i have. This also matches the SN75185 chip that it's designed as drop in replacement for.
good:
https://electronics.stackexchange.com/a/649122
https://www.ti.com/lit/ds/symlink/tl145406.pdf
Revisions
2024-05-22
Pending, ffs lets hope this is it. Switched to the SN75185 part and updated the layout.
2024-05-12
Discovered the MAX3185 datasheet has pins 13 and 16 swapped on it. All the CAD models have the same swap. After cutting and fixing this, the board works as expected.
Will need to do a respin once Maxim/Analog Devices gets back to me.
2024-05-01
PCB needs to be respun IO ports are reversed on the IO lines of the level converter.
Change the switch to use RS232 levels vs 5v TTL levels for 2-4.
Production Testing
With Quantar set to originate clock
- plug in board, relay should activate
- Verify clock is seen on the TXCLK pin 3 (W/Green) of J2 or pin 1 (W/Orange) of J3.
- Close SW3 and check for clock on RXCLK (W/Orange) of J2
- Connect using straight through cable from cross port to astrotac v.24 port set to clock from DCE. Check that it is down, but you see data on the TXD line.
- close SW1 to enable CTS and check that Pin 42 CTS of J1 is low and that CTS on J2 is RS232 level high (4-10v)
- close SW2 to tie RTS and CTS and check that RTS and CTS are low on J1 (41 and 42)
- close SW4 to assert CD and see that the link is up between quantar and astrotac.
This should verify everything other than TXCLK input from DCE.
- ↑ this needs the CD line asserted
